CS501 Final term Past Papers important solve Question

  CS501 Final term Past Papers important solve Question 4. Does DMA affect the relationship b/w the memory system and CPU? Explain with reas...

 CS501 Final term Past Papers important solve Question

4. Does DMA affect the relationship b/w the memory system and CPU? Explain with reasons. (5)

5. Diff b/w sender and receiver overhead related to network. (3)

6. What are functions of valid bit in Associative mapping strategy for cache? (3)
Answer:

 (Page 359) A given block in cache is identified uniquely by its main memory block number, referred to as a tag, which is stored inside a separate tag memory in the cache. To check the validity of the cache blocks, a valid bit is stored for each cache entry, to verify whether the information in the corresponding block is valid or not.
7. Recode the integer 484 according to booth procedure. (3)

8. Write structural RTL of ret ra. (3)
Answer:

 (Page 165)
32
9. Consider a 64KB directed mapped cache with a line length of 32 bytes. Determine the number of
bits in the address that refers to the byte within a cache line. (2)

10. What attributes should a device have in order to be qualified as a master device? (2)

11. What functions are provided by a typical memory cell? (2)

12. What is format of 2-address instruction set? (2)
Answer:

 (Page 35)
1. Where is TCP/IP is used.

2. Usage of DMA

3. How to right RTL
Answer:

 (Page 66) RTL stands for Register Transfer Language. The Register Transfer Language provides a formal way for the description of the behavior and structure of a computer. The RTL facilitates the design process of the computer as it provides a precise, mathematical representation of its functionality. In this section, a Register Transfer Language is presented and introduced, for the SRC (Simple „RISC‟ Computer), described in the previous discussion.
4. What you mean by ISA (Instruction Set Architecture)

33
5. Define the different types of Instructions used in FALCON-E
Answer:

 (Page 125) Four different instruction formats are supported by the FALCON-E. These are
Type A instructions The type A instructions have 5 bits reserved for the operation code (abbreviated op-code), and the rest of the bits are either not used or specify a displacement.
Type B instructions The type B instructions also have 5 bits (27 through 31) reserved for the op-code. There is a register operand field, ra, and an immediate or displacement field in addition to the op-code field.
Type C instructions Type C instructions have the 5-bit op-code field, two 3-bit operand registers (rob is the source register, ra is the destination register), a 17-bit immediate or displacement field, as well as a 3-bit function field. The function field is used to differentiate between instructions that may have the same op-code, but different operations.
Type D instructions Type D instructions have the 5-bit op-code field, three 3-bit operand registers, 14 bits are unused, and a 3-bit function field.
6. Uni-bus interaction with I/O subsystem
8. Define one benefit and one Drawback of Cache.

9. Define different level of RAID and What are the similarities at Level 2 and Level 3 of the RAID?
Answer:

 (Page 329)
RAID Level 0 • Not a true member of the RAID family. • Does not include redundancy to improve performance. • In few applications, capacity and performance are primary concerns than improved reliability. So, RAID level 0 is used in such applications. • The user and system data are distributed across all the disks in the array. 34 • Notable advantage over the use of a single large disk. • Two requests can be issued in parallel, reducing the I/O queuing time.
Similarities between RAID Levels 2 and 3 • Make use of parallel access techniques. • All member disks participate in execution of every request. • Spindles of the individual drives are synchronized • Data striping is used. • Strips are as small as a single byte or word.
RAID Level 4 • Make use of independent access technique. • Data striping is used. • A bit-by-bit parity strip is calculated across corresponding strip on each data disk. • Involves a write penalty when an I/O write request of small size is performed. • To calculate the new parity, the array management software must read the old user parity strip.
RAID Level 5 • Organized in a similar fashion to RAID 4 • The only difference is that RAID 5 distributes the parity strips across all disks.
Q1 ( Marks: 5 )
Consider a 4 way set-associative cache with 256KB capacity and 32 byte lines
a) How many sets are there in the cache?
b) How many bits of address are required to select a set in cache?

Q2 convert the hexadecimal number B316 to base 10 5Marks
Answer:

 (Page 334) According to the above algorithm, X=0 X= by (=11) =11 X=16*11+3= 179 Hence B316=17910
35
Q3 what do you know about " booth pair recording 3marks
Answer:

 (Page 342) The Booth Algorithm makes multiplication simple to implement at hardware level and speed up the procedure. This procedure is as follows: 1. Start with LSB and for each 0 of the original number, place a 0 in the recorded number until a 1 in indicated. 2. Place a 1 for 1in the recorded table and skip any succeeding 1‟s until a 0 is encountered. 3. Place a 0 with 1 and repeat the procedure.
Q.4 assembler symbol table note.3-marks:
Answer:

 Symbol table contains information to locate and relocate symbolic definitions and references. The assembler creates the symbol table section for the object file. It makes an entry in the symbol table for each symbol that is defined or referenced in the input file and is needed during linking. Symbol Table corresponds to the storage of all program variables, labels and data values in a data structure at the implementation level. The Symbol Table includes data members, data addresses and labels with their respective values.
Q.5 configuration of 1x8 memory cell .3marks

Q.6 Single detached DMA 5marks
Answer:

 (Page 318) When a particular I/O module needs to read or write large amounts contiguous data it requests the processor for direct memory access. If permission is granted by the processor, the I/O module sends the read or writes address and the size of data needed to be read or written to the DMA module. Once the DMA module acknowledges the request, the I/O module is free to read or write its contiguous block of data from or onto main memory. Even though in this situation the processor will not be able to execute while the transfer is going on (as there is a just a single bus to facilitate transfer of data), DMA transfer is much faster than having each word of memory being read by the processor and then being written to its location.
Q.7 what is hardest 2 marks

Q.8 difference bow connection oriented and connection less

36
Q1 what is assembler and what is it important in assembly language (2)

Q2 what is program instruction control? (2)
Answer:

 click here for detail the program control instructions direct the flow of a program and allow the flow of the program to change. A change in flow often occurs when decisions, made with the CMP or TEST instruction, are followed by a conditional jump instruction.
Q3 define virtual memory (2)

Q4 difference between higher level language and assembler (3)
Answer:

 (Page 26) Higher-level languages may not be appropriate for programming special purpose or embedded processors that are now in common use in various appliances. This is because the functionality required in such applications is highly specialized. In such a case, assembly language programming is required to implement the required functionality.
Q5define ISA

Q6 convert (390)10 into base 16 (5)
Answer:

 (Page 335) According to the above algorithm 390/16 =24(rem=6), x0=6 24/16= 1(rem=8), x1=8, x2=1 Thus 39010=18616
Q7 define pipelining (5)
Answer:

 (Page 202) Pipelining is a technique of overlapping multiple instructions in time. A pipelined processor issues a new instruction before the previous instruction completes. These results in a larger number of operations performed per unit of time. This approach also results in a more efficient usage of all the functional units present in the processor, hence leading to a higher overall throughput. As an example, many shorter integer instructions may be executed along with a longer floating point multiply instruction, thus employing the floating-point unit simultaneously with the integer unit. 37
Q8 define the type of error control (5)
Answer:

 (Page 328) There are two main issues in error control: 1. Detection of Error 2. Correction of Error For detection of error, we just need to know that there exists an error. When the error is detected then the next step is to ask the source to resend that information. This process is called automatic request for repeat. In some cases, there is also possibility that redundancy is enough and we reconstruct and find out exactly which particular bits are in error. This is called error correction.
Q9 define booth recording (2)

1. What is the purpose of control unit? 2

2. Booth pair Recording? 2

3. Which technique allows certain hardware subsystems within a computer to access system memory for
read/write independently of the main CPU?
Answer:

 click here for detail Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card.
4. 64KB direct-mapped cache line length 32, determine number of bits in the address?

5. Similarities and diff. between RAID level 4 and 5
Answer:

 (Page 332)
RAID Level 4 • Make use of independent access technique. • Data striping is used. • A bit-by-bit parity strip is calculated across corresponding strip on each data disk. • Involves a write penalty when an I/O write request of small size is performed. • To calculate the new parity, the array management software must read the old user parity strip. 38
RAID Level 5 • Organized in a similar fashion to RAID 4 • The only difference is that RAID 5 distributes the parity strips across all disks.
6. Consider a 4-way set-associative cache with 256KB capacity and 32-byte lines
I. find sets in the cache
ii. and bit address required to select a set.

7. Advantage of linker in the development of assembly language program

8. Steps used for floating point addition and subtraction.
Answer:

 (Page 00) The following are the steps for floating-point addition and subtraction. Unpack sign, exponent and fraction fields Shift the significand Perform addition Normalize the sum Round off the result Check for overflow
9. Diff b/w distributed computing and computer Network and classifications of networks
Answer:

 (Page 386)
Difference between Distributed Computing and Computer Networks In distributed computing, all elements which are interconnected operate under one operating system. To a user, it appears as a virtual unit-processor system. In a computer network, the user has to specify and log in on a specific machine. Each machine on the network has a specific address. Different machines communicate by using the network which exists among them.
Classification of Networks We can classify a network based on the following two parameters: • The number and type of machines to be interconnected • The distance between these machines
10.software polling and drawbacks of software polling and daisy chain
Answer:

 (Page 283)
Software Poll CPU polls to identify the interrupting module and branches to an interrupt service routine on detecting an interrupt. This identification is done using special commands or reading the device status register. Special command may be a test I/O. In this case, CPU raises test I/O and places the address of a particular I/O module on the address line. If I/O module sets the interrupt then it responds positively. In the case of an addressable status register, the CPU reads the status register of each I/O module to identify the interrupting module. Once the correct module is identified, the CPU branches to a device service routine which is specific to that particular device. 39
Disadvantages of Software Poll and Daisy Chain The software poll has a disadvantage is that it consumes a lot of time, while the daisy chain is more efficient. The daisy chain has the disadvantage that the device nearest to the CPU would have highest priority. So, usually those devices which require higher priority would be connected nearer to the CPU. Now in order to get a fair chance for other devices, other mechanisms could be initiated or we could say that we could start instead of device 0 from that device where the CPU finishes the last interrupt and could have a cyclic provision to different devices.
11.cache and its management

12. compare RISC and CISC

What is DMA?

Differentiate between throughput and latency?
Answer:

 (Page 203) Latency is defined as the time required to process a single instruction, while throughput is defined as the number of instructions processed per second. Pipelining cannot lower the latency of a single instruction; however, it does increase the throughput. With respect to the example discussed earlier, in a non-pipelined machine there would be one instruction processed after an average of 5 cycles, while in a pipelined machine, instructions are completed after each and every cycle (in the steady-state, of course!!!). Hence, the overall time required to execute the program is reduced.
Describe six attributes of SRC Processor?
Answer:

 (Page 46) • The SRC contains 32 General Purpose Registers: R0, R1, …, R31; each register is of size 32-bits. • Two special purpose registers are included: Program Counter (PC) and Instruction Register (IR) • Memory word size is 32 bits • Memory space size is 232 bytes • Memory organization is 232 x 8 bits, this means that the memory is byte aligned • Memory is accessed in 32 bit words ( i.e., 4 byte chunks) • Big-endian byte storage is used
40
Briefly Describe Classification of Networks?
Answer:

 (Page 387)
Classification of Networks We can classify a network based on the following two parameters: • The number and type of machines to be interconnected • The distance between these machines Based on these two parameters, we have the following type of networks:
SAN (System/Storage Area Network) It refers to a cluster of machines where large disk arrays are present. Typical distances could be tens of meters.
LAN (Local Area Network) It refers to the interconnection of machines in a building or a campus. Distances could be in Kilometers.
WAN (Wide Area Network) It refers to the interconnection between LANs.
Write note on Pipelining?

What is virtual memory?

How does work Associative Mapping?
Answer:

 (Page 359) In this technique, block of data from main memory can be placed at any location in the cache memory. A given block in cache is identified uniquely by its main memory block number, referred to as a tag, which is stored inside a separate tag memory in the cache. To check the validity of the cache blocks, a valid bit is stored for each cache entry, to verify whether the information in the corresponding block is valid or not. Main memory address references have two fields. • The word field becomes a “cache address” which specifies where to find the word in the cache. • The tag field which must be compared against every tag in the tag memory.
How overflow is represented in case of floating point?
Answer:

 (Page 348) e^= 255, denotes numbers with no numeric value including + ∞ and - ∞ and called Not-a-Number or Nan. In computers, a floating-point number of ranges from 1.2 × 10-38 ≤ x ≤ 3.4 × 1038 can be represented. If a number does not lie in this range, then overflow can occur. Overflow occurs when the exponent is too large and cannot be represented in the exponent field.