CS501 Final term Past Papers important solve Question diff bow serial and parallel transfer Answer: (Page 396) Serial Transfer, or se...
CS501 Final term Past Papers important solve Question
diff bow serial and parallel transfer
Answer:
(Page 396)
Serial Transfer, or serial communication of data between the CPU
and the I/O devices, refers to the situation when all the data bits in a
"piece of information", (which is a byte or word mostly), are transferred
one bit at a time, over a single pair of wires.
Parallel Transfer, or parallel communication of data between the
CPU and the I/O devices, refers to the situation when all the bits of data (8
or 16 usually), are transferred over separate lines simultaneously, or in
parallel.
configuration of 1x8 memory
Answer:
(Page 351)
Consider a 4-way set-associative cache with 256KB capacity and 32-byte lines
a) How many sets are there in the cache?
b) How many bits of address are required to select a set-in cache?
5)
difference bow connection oriented and connection less
Answer:
(Page 394)
Connection Oriented Communication • In this method, same path is always
taken for the transfer of messages. • It reserves the bandwidth until the
transfer is complete. So, no other server could use that path until it becomes
free. • Telephone exchange and circuit switching is the example of connection-oriented
communication.
Connection less Communication • Here message is divided into packets
with each packet having destination address. • Each packet can take different
path and reach the destination from any route by looking at its address. •
Postal system and packet switching are examples of connection less
communication.
21
compare 1D AND 2D
Answer:
(Page 351)
write RTL for five instructions
move R3,45
In R3,57
OUT R6 15
RET R3
ANDI R5, R4. 5
Answer:
(Page 93)
move R3,45 R [3] ← 56
In R3,57 R [3] ← IO [57]
OUT R6 15 IO [16] ← R [6]
RET R3 PC ← R [3]
ANDI R5, R4. 5 R [5] ← R [4] & 5
22
Differentiate b/w RISC n CISC according to their instruction size and
hardware, software? 5 marks.
Answer:
Click here for
detail
CISC RISC Emphasis on hardware Emphasis on Software Include multi-clock
Include Single-clock complex instructions Reduced instructions only memory to memory:
Registers to Register: "LOAD" and "STORE “incorporated in
instructions "LOAD" and "STORE “are independent instructions
Small code sizes Large code sizes high cycles per second Low cycles per second
Transistors used for storing Spend more transistors on memory registers
23
A hard disk with 5 platters has 1024 tracks per platter,512 sectors per
track and 512 bytes/sector. What
is the total capacity of the disk? 5 marks.
Answer:
(Page 324) 512
bytes x 512 sectors=0.2MB/track 0.2MB x 1024 tracks=0.2GB/platter Therefore the
hard disk has the total capacity of 5 x 0.2=1GB
What is the function of Control unit? 3 marks.
What is the difference between control unit n data path? 2 mark
Answer:
(Page 150) The
data path design involves decisions like the placement and interconnection of
various registers, the type of flip-flops to be used and the number and kind of
the interconnection buses. The control unit design is a rather tricky process
as it involves timing and synchronization issues besides the usual combinational
logic used in the data path design.
What is the working of DMA controller? 5 marks
Answer:
(Page 314) A
DMA controller could be a CPU in itself and it could control the total activity
and synchronize the transfer of data”. DMA could be considered as a technique
of transferring data from I/O to memory and from memory to I/O without the
intervention of the CPU. The CPU just sets up an I/O module or a memory
subsystem, so that it passes control and the data could be passed on from I/O
to memory or from memory to I/O or within the memory from one subsystem to
another subsystem without interaction of the CPU. After this data transfer is
complete, the control is passed from I/O back to the CPU.
Define 64K x 1 static RAM chip? 5 marks.
Answer:
(Page 352)
24
Format of the 1-Address instruction set-----2 Marks
Answer:
(Page 35)
What attributes should have a device to qualify in order to be master device
---- 2 Marks
Answer:
(Page 317) A
Master must have the capability to place addresses on the address bus and
direct the bus activity during a bus cycle.
A network is suing the Bus topology if we replace the bus with switch what
change will be take effects by
this configuration…. 2 Marks
What is ISA explain…. 2 marks
Answer:
(Page 28) This
set of instructions or operations and the resources together form the
instruction set architecture (ISA). It is the ISA, which serves as an interface
between the program and the functional units of a computer, i.e., through
which, the computer’s resources, are accessed and controlled.
Explain the relationship between the Hard disk tracks, cylinders and
sectors…3 marks
Answer:
(Page 323) A
hard disk is the most frequently used peripheral device. It consists of a set
of platters. Each platter is divided into tracks. The track is subdivided into
sectors. To identify each sector, we need to have an address. So, before the
actual data, there is a header and this header consisting of few bytes like 10
bytes. Along with header there is a trailer. Every sector has three parts: a
header, data section and a trailer.
Explain 1bit half adder function ……3 marks
Answer:
(Page 339) It
takes two 1-bit inputs x and y and as a result, we get a 1-bit sum and a 1-bit
carry. This circuit is called a half adder because it does not take care of
input carry. In order to take into account, the effect of the input carry, a
1-bit full adder is used which is also shown in the figure. We can add two
m-bit numbers by using a circuit which is made by cascading m 1-bit full
adders. 25
SRS assembly program for the following expiration.5 Marks
Z = 13(A+B)-32(c-58)
Answer:
(Page 57) ld.
R1, c ; c is a label used for a memory location sub R3, R1, 58 ; R3 contains
(c-58) shul R7, R3, 5 ; R7 contains 32(c-58) ld. R4, A ld. R5, B add R6, R4, R5
; R6 contains (A+B) Notice that the SRC does not have a multiply instruction.
We will make use of the fact that multiplication with powers of 2 can be
achieved by repeated shift left operations. But in the given example 13 is not
directly is a power of 2. So, you need to make it power of 2. 13(A+B) = 8(A+B)
+ 4 (A+B) + (A+B) Suppose we place A+B in some register say R6. Shel R7, R6, 3;
;8 (A+B) Shel R8, R6, 2; ;4 (A+B) Add R10, R8, R7; ;8 (A+B) + 4 (A+B) Add R11,
R6, R10; ;8 (A+B) + 4 (A+B) + (A+B)that is equal to 13((A+B)) sub R12, R7, R11 set
R12, z ; store the result in memory location z
Latency of the ram is 30ns , if the time charge is 10ns and data pre change
is 3 byte then find the band
width…5 Marks
Compare the 1 x 8-bit Memory (1D) and 4 x 8 Memory (2D) 5 marks
26
Consider a 64KB direct-mapped cache with a line length of 32 bytes.
(5 marks)
a. Determine the number of bits in the address that refer to the byte within
a cache line.
b. Determine the number of bits in the address required to select the cache
line
Comparisons of FALCON-A and SRC (5 marks)
Answer:
(Page 272)
Comparisons of the SRC and
FALCON-A Examples The FALCON-A and SRC programmed I/O examples
discussed are similar with some differences. In the first example discussed for
the SRC (i.e. Character output), the control signal responsible for data
transfer by the CPU is the ready signal while for FALCON-A Busy (active low)
signal is checked. In the second example for the SRC, the instruction set,
address width and no. of lines on address is different. Although different
techniques have been used to increase the efficiency of the programmed I/O,
overheads due to polling cannot be completely eliminated.
How many platters are required for a 40GB disk if there are 1024
bytes/sector, 2048 sectors per track
and 4096 tracks per platter (5)
What is difference between hard disk, cylinder, sector (3 marks)
How to Virtual Memory work? Briefly define? (3 marks)
Differences between RAID2 and RAID 3 (3 marks)
What is Cache? How does it work? (3 marks)
Answer:
(Page 356)
Cache by definition is a place for safe storage and provides the fastest
possible storage after the registers. The cache contains a copy of portions of
the main memory. When the CPU attempts to read a word from memory, a check is
made to determine if the word is in the cache. If so, the word is delivered to
the CPU. If not, a block of the main memory, consisting of some fixed number of
words, is read into the cache and then the word is delivered to the CPU.
27
Cache Management (2 marks)
Answer:
(Page 339) To
manage the working of the cache, cache control unit is implemented in hardware,
which performs all the logic operations on the cache. As data is exchanged in
blocks between main memory and cache, four important cache functions need to be
defined. Block Placement Strategy Block Identification Block Replacement Write
Strategy
What is EPROM (3 marks)
Answer:
(Page 356) Erasable
Programmable Read-only Memory or EPROM chips have quartz windows and by
applying ultraviolet light erase the data can be erased from the EPROM. Data
can be restored in an EPROM after erasure. EPROMs are more expensive than PROMs
and are generally used for prototyping or small-quantity, special purpose work.
What is difference between comma and semi-colon (2 marks)
Answer:
(Page 8-163)
Comma „, ‟ indicates that these two instructions are concurrent and only one of
them would execute at a time.
Comments are indicated by a
semicolon (;) and can be placed anywhere in the source file. The
FALSIM assembler ignores any text after the semicolon.
1. What is the difference between CPU Register and cache.
Answer?
Rep
2. How do you refer register in RTL.
Answer?
Rep
3. What are the advantages of RAID?
Answer:
(Page 329) The
main advantage of having an array of disks is that we could have a simultaneous
I/O request. Latency could also be reduced. 28
4. Give two advantages of virtual memory.
5. Explain relationship between Hard disk, tracks, cylinders, sectors.
6. Give difference between spatial Locality and Temporal correlation.
7. Write about single server model and give example.
Answer:
(Page 381)
Consider a black box. Suppose it represents an I/O controller. At the input, we
have arrival of different tasks. As one task is done, we have a departure at
the output. So, in the black box, we have a server. Now if we expand and
open-up the black box, we could see that incoming calls are coming into the
buffer and the output of the buffer is connected to the server. This is an
example of “single server model”.
8. Write structural RTL Call ra, rob.
Answer:
(Page 165)
10. Difference between Internal and external fragmentation.
11. Give all steps of Integer division algorithm to divide 45 by 5 in 10
base systems.
Answer:
(Page 343)
There are steps of integer division present on page number 343 of course
handouts. But none the less I am going to explain its working. Divide 47
decimal with 5 decimals. 47 and 5 is converted into binary 29 47 = 000000
101111 In these the left six bits are the upper half of dividend and the right
ones are the lower half of the dividend. 5 = 000101 We use capital “D” for
dividend and small “d” for divisor. D = 000000 101111 d = 000101 First we shift
left one bit the value of Dividend and add zero. D = 0 000001 011110 d = 000101
(Now we if the result is negative than we append “0” to the quotient and if it
is positive than we replace the upper half the dividend with the positive
result and append “1” to the quotient.) D = 0 000001 011110 d = 000101 q = 0
The result is negative so we append “0” to the quotient D = 000010 111100 d =
000101 q = 00 The result is again negative so we append “0” to the quotient D =
000101 111000 d = 000101 -------------- = 000000 q = 001 The result is positive
so we append “1” to the quotient and replace the result with the upper half of
the dividend. Now D = 000000 111000 D = 000001 110000 d = 000101 q = 0010 The
result is negative so we append “0” to the quotient 30 D = 000011 100000 d =
000101 q = 00100 The result is again negative so we append “0” to the quotient
D = 000111 000000 d = 000101 -------------- = 000010 q = 001001 The result is
positive so we append “1” to the quotient. Remainder = 000010 = 2 decimal
Quotient = 001001 = 9 decimal
2. An IO system with single disk gets 100 IO requests/sec. Assume the
average time for a disk to
service an IO request is 6ms. What is utilization of the IO system? (5)
Answer:
(Page 382)
Time for an I/O request = 6ms =0.006sec Server utilization = 100 x 0.006 = 0.6
3. What are characteristics of D-flip-flop? Draw truth table. (5)
Answer:
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