CS501 Final term Past Papers important solve Question How many drives do you need a minimum to form RAID 0? (2 marks) 0 Only 1 Minimum ...
CS501 Final term Past Papers important solve Question
How many drives do you need a minimum to form RAID 0? (2
marks)
0
Only 1
Minimum 2
Maximum 2
Answer:
click here for
detail
Minimum 2 To establish a RAID 0 volume, a minimum of at least 2 hard
disk drives are required. Unlike RAID 1, the number of drives used in the array
can be an odd or even number.
What function is performed by the reset operation of a processor?
What are the two types of reset
operations?
Answer:
(Page 194-195)
The two essential features of a reset instruction are clearing the control step
counter and reloading the PC to a predefined value.
Hard Reset the SRC should perform a hard reset upon receiving a start (Start)
signal. This initializes the PC and the general registers.
Soft Reset the SRC should perform a soft reset upon receiving a reset (rest)
signal. The soft reset results in initialization of PC only. The reset signal
in SRC is assumed to be external and asynchronous.
Q2 What do you know about Hard disk.
Answer:
(Page 323)
Peripheral devices connect the outside world with the central processing unit
through the I/O modules. One important feature of these peripheral devices is
the variable data rate. Peripheral devices are important because of the
function they perform. A hard disk is the most frequently used peripheral
device. It consists of a set of platters. Each platter is divided into tracks.
The track is subdivided into sectors. To identify each sector, we need to have
an address. So, before the actual data, there is a header and this header
consisting of few bytes like 10 bytes. Along with header there is a trailer.
Every sector has three parts: a header, data section and a trailer. 11
Q 3: - Convert (0.23)10
to the base 2 address 2Marks
Answer:
(page 336)
0.23*2=0.46, f-1=0
0.46*2=0.92, f-2=0
0.92*2=1.84, f-3=1
0.84*2=1.68, f-4=1
0.68*2=1.36, f-5=1, …
Thus 0.2410 = (0.00111) 2
Question no 4
What is meant by Packet switching
Answer:
(Page 387) A
block (an appropriate number of bits) of data is called a packet. Transfer of
data in the form packets through different paths in a network is called packet
switching. Additional bits are usually associated with each packet. These bits
contain information about the packet. These additional bits are of two types:
header and trailer. As an example, a packet may have the form shown below: If
we use a 1- bit header, we may have the following protocol: Header = 0, it
means it is a request Header = 0, Reply By reading these header bits, a machine
becomes able to receive data or supply data. To transfer data by using packets
through hardware is very difficult. So, all the transfer is done by using
software. By using a greater number of bits, in a header, we can send more
messages. For example, if n bits are used as header then 2n is the number of messages
that can be transmitted over a network by using a single header. For a 2-bit
header: we may have 4 types of messages: 00= Request 01= Reply 10= Acknowledge
request 11= Acknowledge reply
Question no 6
Classification of fiber optics mode multimode and mono mode?
Question no 7
Consider a 64KB direct-mapped cache with a line length of 32 bytes. (5
marks)
a. Determine the number of bits in the address that refer to the byte within
a cache line.
b. Determine the number of bits in the address required to select the cache
line
12
Answer:
(Page 375)
Address breakdown n=log2 of
number of bytes in line m=log2 of
number of lines in cache a. For the given cache, the number of bits in the
address to determine the byte within the line= n = log232 = 5 b. There are 64K/32= 2048 lines in the
given cache. The number of bits required to select the required line = m =log22048 = 11 Hence n=5 and m=11
Question no 8
If a DRAM has 512 rows and its fresh time is 9ms. What should be the
frequency of row refresh operation
on the average?
Answer:
(Page 371)
Refresh time =9ms Number of rows =512 Therefore we have to do 512 row refresh
operations in a 9 MS interval, in other words one row refresh operation every (9*10-³)/512=1.76
* 10-5 second
Question
Structural RTL for not instruction not ra, rob
Answer:
(Page 160)
Question
why we use matrix in decoder
Answer:
(Page 352) A
typical one level decoder has n inputs and 2n output, using one level of gates, each with a fan-in
of n. Two level decoders are limited in size because of high gate fan-in. In
order to reduce the gate fan-in to a value of 8 or 6, tree and matrix decoders
are utilized.
41. What are the functions of memory cell? 2 marks
Answer:
(Page 351) A
memory cell provides four functions: Select, Data In, Data Out, and Read/Write.
Data In means input and Data Out means output. The select signal would be
enabled to get an operation of Read/Write from this cell.
What is Packet Switching? 2 marks
43. How we can specify registers in
RTL? Give an example? 2 marks
Answer:
(Page 66)
Specifying Registers The format used to specify registers is Register
Name<register bits> For example, IR<31.0> means bits numbered 31 to
0 of a 32-bit register named “IR” (Instruction Register). 44. What is seek
time of hard disk? 3 marks
Answer:
(Page 323)
When it is required to read data from a particular location of the disk, the
head moves towards the selected track and this process is called seek. The disk
is constantly rotating at a fixed speed. After a short time, the selected
sector moved under the head. This interval is called the rotational delay. On
the average, the data may be available after half a revolution. Therefore, the
rotational latency is half revolution. The time required to seek a particular
track is defined by the manufacturer. Maximum, minimum and average seek times
are specified. Seek time depends upon the present position of the head and the
position of the required sector. For the sake of calculations, we will use the
average value of the seek time. 45. Differences between RAID2 and RAID 3? 3
marks
Answer:
(Page 331) •
In RAID 2, error-correcting code is calculated across corresponding bits on
each data disk. • RAID 3 requires only a single redundant disk. • Instead of an
error-correcting code, a simple parity bit is computed for the set of
individual bits in RAID 3 46. What are three main functions of control Unit?
3marks
Answer:
click here for
detail 1. It directs the entire computer system to carry out stored program
instructions. 2. It must communicate with both the arithmetic logic unit (ALU)
and the main memory. 3. It instructs the ALU on arithmetic operations to be
performed. 14
47. Difference between Spatial Locality and Temporal Correlation? 3 marks
48. How shift instructions are
useful? When we use them? 3 marks
49. Assume there is an accumulator-based
machine in which there are eight general purpose registers of
the CPU. Each register is 16-bits in length. Also, there are two additional
16-bit system registers which
are the program counter (PC) and the instruction register (IR). The size of
the memory word is 16-bit.
Using your knowledge of processor design process, answer the following
question.
Which name convention will you use to name each of these eight general
purpose registers?
What is the available memory space size knowing that memory word is 16 bits?
5 marks
Answer:
(Page 112)
a) As the length of register is 16-bit so we use Little-endian name
convention
b) memory word is 16-bit so the available memory space size is 216 bytes 50. Find the
bandwidth of a memory system that has a latency of 30ns, a pre charge time of
10ns and
transfers 3 bytes of data per access. 5 marks
51. Using radix conversion algorithm
converts 39210 to
base 16… 5 marks
Answer:
52. Differentiate
between internal and external fragmentation 5
15
How can overflow occur in floating point? (2 Marks)
Answer:
(Page 348)
Overflow occurs when the exponent is too large and cannot be represented in the
exponent field.
What is Packet Switching? (2 Marks)
Difference between Eagle and modified Eagle (2 Marks)
Answer:
(Page 120) The
modified EAGLE is an improved version of the processor EAGLE. As we have
already discussed, there were several limitations in EAGLE, and these have been
remedied in the modified EAGLE processor.
Why we represent sometime some numbers in sign magnitude form.
Answer:
(Page 336) •
This is the simplest form for representing a signed number • A symbol
representing the sign of the number is appended to the left of the Number •
This representation complicates the arithmetic operations
(3 Marks Questions)
What is 4-address instruction set and when it use?
Answer:
(Page 36)
16
Difference between virtual address and physical address
Answer:
(Page 321)
Virtual Address: Virtual address is generated be the logical by the
memory management unit for translation.
Physical Address: Physical address is the address in the memory.
Why Transaction Lock Aside Buffer is used? How it is implemented inside CPU?
Answer:
(Page 368)
Identifying a particular page in the virtual memory requires page tables (might
be very large) resulting in large memory space to implement these page tables.
To speed up the process of virtual address translation, translation Lookaside
buffer (TLB) is implemented as a small cache inside the CPU, which stores the
most recent page table entry reference made in the MMU. Its contents include •
A mapping from virtual to physical address • Status bits i.e. valid bit, dirty
bit, protection bit It may be implemented using a fully associative
organization
What is sender overhead and receiver overhead in computer networks?
Answer:
(Page 388)
Sender overhead It is the time for the processor to inject message in to
the network.
Receiver overhead It is the time for the processor to pull the message
from the network.
5 Marks Questions
Find the average access time of a level of memory hierarchy if the hit rate
is 80%. The memory access
takes 12ns on a hit and 100ns on a miss.
Answer:
(Page 372) 17
What is difference of instruction in machine with and without Pipeline?
Answer:
(Page 202)
Convert (0.23)10 to
the base 2 address.
Consider a 4-way set-associative cache with 256KB capacity and 32-byte lines
a) How many sets are there in the cache?
b) How many bits of address are required to select a set-in cache?
Q 1: Consider 64KB direct mapped cache, line length 32 bytes, and
find the number of bits in the
address. 2
18
Q 2: Define virtual memory 2
Answer:
(Page 364)
Virtual memory acts as a cache between main memory and secondary memory. Data
is fetched in advance from the secondary memory (hard disk) into the main memory
so that data is already available in the main memory when needed. The benefit
is that the large access delays in reading data from hard disk are avoided.
Q 3: What does the RTL expression M [1234] means 2
Answer:
click here for
detail The RTL expression [M (1234)] means the contents of memory whose
location (i.e., address) is 1234. Or, sometimes expressed as 0x1234 to denote
hex.
Q 4: What are the sectors of the hard disk? 2
Answer:
(Page 323) A
hard disk is the most frequently used peripheral device. It consists of a set
of platters. Each platter is divided into tracks. The track is subdivided into
sectors. To identify each sector, we need to have an address.
Q 5: Why MIPS is not very accurate basis for comparison of different
processes. Write formula of MIPS.
3
Answer:
(Page 45) MIPS
= IC/ (ET x 106) This
measure is not a very accurate basis for comparison of different processors.
This is because of the architectural differences of the machines; some machines
will require more instructions to perform the same job as compared to other
machines. For example, RISC machines have simpler instructions, so the same job
will require more instructions. This measure of performance was popular in the
late 70s and early 80s when the VAX 11/780 was treated as a reference.
Q 6: Record the integer 485 according to the BOOTH procedure 3
Answer:
(Page 343)
Solution Original number: 00111100101=256+128+64+32+4+1=485 Recoded Number: _ _
_ 01000101111=+512-32+8-4+2-1=485
Q 7: Find out sign, significand and exponent of -7×10-4. 3
Answer:
Sign = -1
Significand= 7 Exponent= -4 Base = 10 19
Q 8: Calculate Bandwidth, given Latency 30ns, per charge time is 10ns and 3
bytes of data per access.
5
Q 9: Convert 0.2310 to
base 2 5
Q 10: Differentiate between internal and external fragmentation 5
Q 11: Solve the instruction z = 5(a-b) +17(c+26) using
1) 1 address instruction
2) 0 address instruction.
(2)
where TCP/IP Used??
Answer:
(Page 396)
Internet uses TCP/IP protocol. In the TCP/IP model, session and presentation
layers are not present, so Store Forward routing is used.
define PROM
(3)
Stages in pipelined SRC
Answer:
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